The present application relates generally to computer system performance adaption. More specifically, the present application is directed to idle-aware margin adaption in a multi-core processing system.
Computer systems can dynamically adjust voltage and frequency settings during execution as part of power management. As one example, dynamic voltage and frequency scaling (DVFS) can be applied to scale voltage and frequency for a processor as part of power management. Typically, a processor that is idling without a workload can operate at a reduced power level achieved by adjusting voltage and/or frequency. However, altering voltage and/or frequency can increase susceptibility to noise events that may impact system reliability. Conversely, operating at a much higher power level than needed reduced power efficiency of the system.